Strain engineering refers to a general strategy employed in semiconductor manufacturing to enhance device performance. Performance benefits are achieved by modulating mechanical strain in the transistor channel, which enhances electron mobility (or hole mobility) and thereby conductivity through the channel.
One particular consideration in using strain engineering in CMOS technologies is that PMOS transistors and NMOS transistors respond differently to different types of strain. Specifically, for industry standard transistors oriented along <110> crystallographic directions, PMOS transistor performance is best served by applying compressive longitudinal strain to the p-channel, whereas NMOS transistor receives benefit from tensile longitudinal strain applied to the n-channel. Different approaches to strain-engineering locally induce strain, allowing both re-channel and p-channel strain to be modulated independently.
NMOS transistors (or NFET) and PMOS transistors (or PFET) thus may include opposing strains for mobility enhancement. Therefore a mobility enhancement for one of the transistors can lead to degradation of performance for the other transistor. To avoid degradation of performance for one of the transistor types, or to obtain mobility enhancement for both at the same time is not straightforward.
One approach involves performing multiple epitaxial growth steps of different types of strained-relaxed buffers and channels. However, these epitaxial growth steps need to be masked such that their growth is performed either on the NFET or on the PFET. These masking steps are both technically challenging and costly.
The migration from conventional planar CMOS technology to non-planar (three dimensional—3D) CMOS technology (also referred to as multi-gate technology, such as for example FINFET) has enabled further device scaling. Due the difference in mobility of the carriers when moving along the sidewall surfaces or the top surface, strain engineering needs to be further improved for non-planar CMOS technology.